The Present invention is related to design the flip flop circuit using implicit pulse triggering, dual edge clocking, rejection of floating node problem and reducing the number of clocked loads scheme for optimizing the power consumption in VLSI system. The proposed IP-DETFF consumes minimum power of 7.410 u,w compared to the existing flip-flops design. The optimization metrices of proposed IP-DETFF are improved as PDP = 0.378 fj, EDP = 0.0193xl0_24and PEP = 0.280 xlO-20. The implicit pulse triggering, rejection of floating node problem, reducing the number of clocked loads and dual edge clocking schemes, reduce the total power consumption of proposed IP-DETFF to7.410 uav and with delay value of 51 ps. The proposed IP-DETFF uses totally 8 numbers of transistors with 2 clocked loads and the total numbers of transistors and clocked loads are greatly reduced in this proposed flip-flop design. This is the major advantage of implicit pulse triggering scheme. This leads to the reduction of power consumption due to clock allocation tree (pcik-tree) and reduces the delay time.

Implicit clock is given to the transistors P2&N2 which supplies the clock signal to latching section. By following the implicit pulse triggering scheme, the clock allocation section is incorporated into the first latching stage itself. This flip-flop is designed by the following approaches such as implicit pulse triggering, dual edge clocking, rejection of floating node problem and reducing the number of clocked loads. Implicit pulsed-Double Edge Triggered Flip-Flop (IP-DETFF) is proposed for low power clocking system.

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